(1) Field of the Invention
The present invention relates to solid-state imaging devices and manufacturing methods thereof, and relates particularly to a solid-state imaging device including plural pixels arranged in a matrix.
(2) Description of the Related Art
A generally known solid-state imaging device includes: a complementary metal oxide semiconductor (CMOS) image sensor and a charge coupled device (CCD) image sensor. Compared to the manufacturing process for the CCD image sensor, the process of manufacturing the CMOS image sensor has an advantage of allowing mounting of plural circuits on a chip because the process of manufacturing the CMOS image sensor is similar to the process of manufacturing an LSI in the CMOS. For example, the CMOS image sensor allows mounting an A/D conversion circuit, a timing generator and the like on the same chip.
On the other hand, in the CMOS image sensor, it is difficult, in some cases, to secure excellent sensitivity characteristics due to decrease in an amount of light incident on a photodiode.
This is because the CMOS image censor requires a plurality of wiring layers (normally, 2 to 4 layers) to be formed so as to carry a plurality of circuits. The metal wiring, blocking the incident light, makes it more difficult for the incident light to reach the photodiode.
Thus, a configuration is suggested which allows efficient collection of incident light using two lenses formed on the photodiode (For example, see: Japanese Unexamined Patent Application Publication No. 2006-114592).
The following will describe a conventional solid-state imaging device.
FIG. 17 is a diagram showing a circuit configuration of a unit cell of a conventional solid-state imaging device.
A solid-state imaging device 500 shown in FIG. 17 includes: a unit pixel 510, a horizontal selection transistor 123, a vertical scanning circuit 140, and a horizontal scanning circuit 141. Note that FIG. 17 shows only one unit pixel 510, but the solid-state imaging device 500 includes a plurality of unit pixels 510 arranged in a matrix.
The unit pixel 510 includes: a photodiode 111, a charge transfer gate 112, a floating diffusion (FD) unit 114, a reset transistor 120, a vertical selection transistor 121, and an amplifying transistor 122.
The photodiode 111 is a photoelectric conversion unit which converts incident light into a signal charges (electrons) and accumulates signal charges resulted from such conversion.
A gate electrode of the charge transfer gate 112 is connected to a read signal line 113. The charge transfer gate 112 transfers the signal charges accumulated in the photodiode 111 to the FD unit 114, based on a read pulse applied to the read signal line 113.
The FD unit 114 is connected to a gate electrode of the amplifying transistor 122.
The amplifying transistor 122 performs impedance conversion to convert the potential variation at the FD unit 114 into a voltage signal, and applies the voltage signal resulted from the conversion to the vertical signal line 133.
A gate electrode of the vertical selection transistor 121 is connected to the vertical selection line 131. The vertical selection transistor 121 turns ON or OFF based on a vertical selection pulse applied to the vertical selection line 131, and drives the amplifying transistor 122 for a predetermined period of time.
A gate electrode of the reset transistor 120 is connected to the vertical reset line 130. The reset transistor 120 resets the potential of the FD unit 114 to the potential of the power line 132, based on a vertical reset pulse applied to the vertical reset line 130.
The vertical scanning circuit 140 and the horizontal scanning circuit 141 scan the plurality of unit pixels 510 once per cycle.
Specifically, the vertical scanning circuit 140 selects, by applying the vertical selection pulse to the vertical selection line 131 for a predetermined period of time in one cycle, a row of unit pixels 510 corresponding to the vertical selection line 131. An output signal (voltage signal) for each of the selected unit pixels 510 is transmitted to the vertical signal line 133.
The horizontal scanning circuit 141 selects a horizontal selection transistor 123 by sequentially applying a horizontal selection pulse to each horizontal selection line 134 for a given period of time.
The selected horizontal selection transistor 123 transmits, to the horizontal signal line 135, an output signal of the vertical signal line 133 connected to the horizontal selection transistor 123.
After the horizontal scanning circuit 141 finishes scanning every unit pixel 510 included in one row, the vertical scanning circuit 140 applies the vertical selection pulse to the vertical selection line 131 in the next row. Next, in the same manner as above, each pixel in another row is scanned.
By repeating this operation to scan every unit pixel 501 once per cycle, the output signals from all the unit pixels 510 are transmitted to the horizontal signal line 135 in a temporal sequence.
FIG. 18 is a cross-sectional view showing a configuration of an imaging area captured by the conventional solid-state imaging device 500.
FIG. 19 is a diagram schematically showing a connection relationship between constituent elements of the unit pixels 510.
As shown in FIG. 18, the solid-state imaging device 500 includes: a semiconductor substrate 201, an insulation layer 202, wirings 203A to 203C, a light-shielding film 204A and 204B, a passivation film 205, an intralayer lens 606, a planarizing film 207, a color filter 208, and a top lens 610.
The photodiode 111 and the FD unit 114 are formed in the semiconductor substrate 201, and the charge transfer gate 112 is formed on the semiconductor substrate 201.
The insulation layer 202 is formed on the semiconductor substrate 201. The wirings 203A to 203C in plural layers are formed inside the insulation layer 202. The wirings 203A to 203C are made of, for example, aluminum.
The light-shielding films 204A and 204B, formed on the wiring 203A and wiring 203B, respectively, prevent incidence of light onto a circuit portion including the transistor. The light-shielding films 204A and 204B are protection films for the wiring formed at the time of manufacturing the wiring.
Normally, in the case where the wirings 203A to 203C are made of a corrosion-prone material such as Cu, a protection film such as a SiN film or a SiON film is formed, at the time of the manufacturing, for the purpose of protecting the wirings 203A to 203C. In this case, the protection film is formed across an entire top surface of the wirings 203A to 203C. However, when the protection film is formed on the photodiode 111, a film stack of a silicon oxide film and a silicon nitride film (protection film) are formed on the photodiode 111. This reflects a light ray incident on the photodiode 111.
Thus, it is preferable that the protection film (silicon nitride film) be removed only from the top of the photodiode 111. In addition, in a region except for the top of the photodiode 111, it is preferable to leave the protection film because the protection film functions as a light-shielding film.
In addition, a photoelectric conversion is caused when incident light 310 leaks into the circuit portion. Electrons generated as a result cause aliasing, which is a noise. By providing light-shielding films 204A and 204B, it is possible to reduce the noise.
The passivation film 205, which is formed on the insulation layer 202, is made of, for example, silicon nitride.
The intralayer lens 606 is formed on the passivation film 205.
The planarizing film 207 is formed on the intralayer lens 606, and is made of, for example, silicon oxide or resin (acrylic resin or fluorinated resin).
The color filter 208 is formed on the planarizing film 207.
The top lens 610 is an on-chip lens formed on the color filer 208.
As shown in FIG. 19, n-type impurity layers included each of the photodiode 111, the FD unit 114, and the reset transistor 120 are provided to be connected by a channel region under the gate electrodes. With this, it is possible to efficiently transfer and erase signal charges.
In addition, the top lens 610 and the intralayer lens 606 collect the incident light 310 to the photodiode 111. The top lens 610 and the intralayer lens 606 are formed at equal intervals at a regular pitch.
Here, in the conventional solid-state imaging device 500, a relative positional relationship in one unit pixel 510, between each of the photodiode 111, the charge transfer gate 112, the FD unit 114, the reset transistor 120, the vertical selection transistor 121, the amplifying transistor 122, the intra-pixel wiring, the top lens 610, and the intralayer lens 606, is common to the plurality of unit pixels 510. That is, the respective constituent elements are placed at equal intervals at the same pitch so as to have the same translational symmetry. This as a result causes the incident light 310 to fall on the photodiode 111 of each unit pixel in the same manner, thus allowing obtaining a satisfactory image which has less unevenness between each unit pixel 510.
On the other hand, as described above, an amplification-type solid-state imaging device such as the CMOS image sensor requires at least two layers, and preferably at least three layers of multilayer wiring, and this results in a thicker configuration to be formed above the photodiode 111. For example, a height from the top surface of the photodiode 111 to the wiring 203C in a top third layer is 3 to 5 μm, which is almost equivalent to a pixel size.
This presents a problem of larger shading in an area closer to a periphery of an imaging area, in a solid-state imaging device which first forms an image through a lens and then captures the image. That is, the light-shielding films 204A and 204B and the wirings 203A to 203C block the light that is obliquely incident, and thereby the amount of light collected to the photodiode 111 is decreased. This causes a problem of significant degradation of image quality.
Thus, a method referred to as pupil correction is used, which is a method of reducing the shading in the area closer to the periphery of the imaging area by correcting positions of openings of the top lens 610 and the light-shielding films 204A and 204B so as to collect the obliquely incident light as well to the photodiode 111. Specifically, the openings of the top lens 610, and the light-shielding films 204A and 204B are provided out of alignment in a direction from which the light enters as viewed from the photodiode 111.
In addition, another method used for preventing decrease in the amount of light incident on the photodiode 111 is to suppress a decrease in the area of the photodiode 111 that is caused by reducing area of the transistor in the unit pixels 510. However, this technique has a limit in maintaining characteristics of the solid-state imaging device.
Suggested in response is a solid-state imaging device having a multi-pixel one-cell configuration in which adjacent unit pixels 510 share the FD unit 114, the amplifying transistor 122, the vertical selection transistor 121, and the reset transistor 120 which have conventionally been provided in each unit pixel 510, except the photodiode 111 and the charge transfer gate 112 that are essential for each unit pixel 510. For the solid-state imaging device having the multi-pixel one-cell configuration, it is possible to reduce the number of transistors and the number of lines per unit pixel. With this, it is possible to secure sufficient area for the photodiode 111 and reduce vignetting due to the wiring, thus allowing an effective response to downsizing of unit pixels.